Packet Dispatcher
PacketDispatcher is a hardware architecture implemented in FPGA for efficiently running functional reactive programs by employing their parallel nature. Such programs consist of streams of data, which are transformed by certain operators. The stream can consist of items of any data type (e.g. boolean, integer, float, array, string, struct), but it must be the same within a stream. To represent data items of various data types in our system, we use packets. A packet consists of the header and the payload. The payload represents the data item itself and may be of any size, which is only limited by the amount of memory available in the system. The header contains metadata which is used to decide how and when a packet will be processed. The structure of the packet header is shown in the table below:
| Field name | Length, bits | Description |
|---|---|---|
id |
10 | Stream id. Allows the processing modules to decide how the packet should be processed. |
seq |
8 | Packet sequence number. Allows modules to establish order across packets of the same stream. |
nc |
1 | No change flag. If it is set, the packet contains not useful data and is needed to signalize about absence of items in a stream at the moment. |
ptr1 |
12 | Pointer to the first payload associated with this buffer. |
ptr2 |
12 | Pointer to the second payload associated with this buffer. Used only for packets that went through the merge or snapshot modules |
Processing packets concurrently in a naive way breaks the semantics of FRP, because it may change the order in which packets arrive to a point of observation. To maintain FPR semantics we introduced the Reorder Engine which . In other words, the system allows to restore the order of packets broken by parallel processing for the streams that are observable.
The system consists a set of modules that are connected to each other by HeaderBus and PayloadBus. Some modules are connected to one of the buses only depending on whether they work with packet header, packet payload or both.
Input peripherals generate packets. Packet payload contains the information about event. For eaxample, GPI (general-purpose intput) may keep track of the state of input pins that belong to it and once it changes, the peripheral issues a packet
Packet headers are dispatched to modules based on their id. If a packet needs to be processed by a map or filter primitives, it is forwarded to the least busy processor module through the Distributor. The processor that receives the header uses its stream id to fetch a proper function from its ROM. It also fetches packet payload from the PayloadBuffer based of the ptr1 and ptr2. After that Processor applies extracted function to packet data and saves the result to a new region in the PayloadBuffer. Then it creates a new packet header with a different stream id, but with the same sequence number. The packet header is issued to the Header Bus for firther processing.
Based on the functional reactive program running on the system, some packets need to be processed by the merge and hold/snapshot engines. However, since the order in which packets arrive to those modules may affect the final result, before going there the order of packets has to be restored based on their sequence number. That is why, all packets comming from soft processor cores must go to the reorder engine first.