Uart

README.md

@@ -5,7 +5,7 @@ This an example RISC-V SoC targeting the Arty-A7 FPGA board. It comprises the
 following features:
 
 * RISC-V debug support (using the [PULP RISC-V Debug Module](https://github.com/pulp-platform/riscv-dbg))
-* A UART (transmit only for now)
+* A UART
 * GPIO (output only for now)
 * Timer
 
@@ -15,7 +15,7 @@ probe is required.
 ## Software Requirements
 
 * Xilinx Vivado - https://www.xilinx.com/support/download.html
-* rv32imc GCC toolchain - lowRISC provide one: 
+* rv32imc GCC toolchain - lowRISC provide one:
   https://github.com/lowRISC/lowrisc-toolchains/releases
 * cmake
 * python3 - Additional python dependencies in python-requirements.txt installed

data/pins_artya7.xdc

@@ -88,7 +88,7 @@ set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { LED[3]
 
 ## USB-UART Interface
 set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
-#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
+set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
 
 ## ChipKit Outer Digital Header
 #set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]

python-requirements.txt

@@ -7,10 +7,10 @@ anytree
 mako
 pyyaml
 wheel
+pyserial
 
 # Development version of edalize until all our changes are upstream
 git+https://github.com/lowRISC/edalize.git@ot
 
 # Development version with OT-specific changes
 git+https://github.com/lowRISC/fusesoc.git@ot
-

rtl/fpga/top_artya7.sv

@@ -7,6 +7,7 @@ module top_artya7 (
     input               IO_RST_N,
     output [3:0]        LED,
     output [11:0]       RGB_LED,
+    input               UART_RX,
     output              UART_TX
 );
   parameter              SRAMInitFile = "";
@@ -22,6 +23,7 @@ module top_artya7 (
     .rst_sys_ni(rst_sys_n),
 
     .gp_o({LED, RGB_LED}),
+    .uart_rx_i(UART_RX),
     .uart_tx_o(UART_TX)
   );
 

rtl/system/ibex_demo_system.sv

@@ -10,6 +10,7 @@ module ibex_demo_system #(
   input logic                 rst_sys_ni,
 
   output logic [GpoWidth-1:0] gp_o,
+  input  logic                uart_rx_i,
   output logic                uart_tx_o
 );
   parameter logic [31:0] MEM_SIZE     = 64 * 1024; // 64 kB
@@ -97,6 +98,8 @@ module ibex_demo_system #(
   logic        dbg_slave_rvalid;
   logic [31:0] dbg_slave_rdata;
 
+  logic uart_irq;
+
   logic rst_core_n;
   logic ndmreset_req;
   logic dm_debug_req;
@@ -218,7 +221,7 @@ module ibex_demo_system #(
      .irq_software_i        (1'b0),
      .irq_timer_i           (timer_irq),
      .irq_external_i        (1'b0),
-     .irq_fast_i            (15'b0),
+     .irq_fast_i            ({14'b0, uart_irq}),
      .irq_nm_i              (1'b0),
 
      .debug_req_i           (dm_debug_req),
@@ -286,6 +289,8 @@ module ibex_demo_system #(
     .device_rvalid_o(device_rvalid[Uart]),
     .device_rdata_o (device_rdata[Uart]),
 
+    .uart_rx_i,
+    .uart_irq_o     (uart_irq),
     .uart_tx_o
   );