[dv] Various fcov fixes and tweaks

lowRISC · Nov 16, 2022 · c48ca23 · c48ca23
1 parent 581f5d4
commit c48ca23
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Showing 3 changed files with 25 additions and 18 deletions.
diff --git a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
@@ -635,11 +635,9 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
     }
 
     priv_mode_exception_cross: cross cp_priv_mode_id, cp_ls_pmp_exception, cp_ls_error_exception {
-      illegal_bins pmp_and_error_exeption_both_or_none =
+      illegal_bins pmp_and_error_exeption_both =
         (binsof(cp_ls_pmp_exception) intersect {1'b1} &&
-         binsof(cp_ls_error_exception) intersect {1'b1}) ||
-        (binsof(cp_ls_pmp_exception) intersect {1'b0} &&
-         binsof(cp_ls_error_exception) intersect {1'b0});
+         binsof(cp_ls_error_exception) intersect {1'b1});
     }
 
     stall_cross: cross cp_id_instr_category, cp_stall_type_id {

diff --git a/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv b/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv
@@ -121,21 +121,20 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
     assign pmp_iside2_nomatch = ~|pmp_iside2_match;
     assign pmp_dside_nomatch  = ~|pmp_dside_match;
 
-    assign misaligned_pmp_err_last = load_store_unit_i.fcov_ls_first_req ?
-                                       load_store_unit_i.data_pmp_err_i :
-                                       misaligned_pmp_err_last;
-
     // Store the Data Channel PMP match info from the first request to calculate boundary cross
     always @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
-        pmp_dside_match_last <= '0;
+        pmp_dside_match_last    <= '0;
+        misaligned_pmp_err_last <= 1'b0;
       end else if (load_store_unit_i.fcov_ls_first_req) begin
-        pmp_dside_match_last <= pmp_dside_match;
+        pmp_dside_match_last    <= pmp_dside_match;
+        misaligned_pmp_err_last <= load_store_unit_i.data_pmp_err_i;
       end
     end
 
     assign pmp_iside_boundary_cross = |(pmp_iside_match ^ pmp_iside2_match);
-    assign pmp_dside_boundary_cross = |(pmp_dside_match ^ pmp_dside_match_last);
+    assign pmp_dside_boundary_cross = |(pmp_dside_match ^ pmp_dside_match_last) &
+                                      load_store_unit_i.fcov_ls_second_req;
 
     for (genvar i_region = 0; i_region < PMPNumRegions; i_region += 1) begin : g_pmp_region_fcov
       pmp_priv_bits_e pmp_region_priv_bits;
@@ -513,7 +512,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
         iff (fcov_csr_write && cs_registers_i.csr_addr_i == CSR_MSECCFG) {
           // Trying to enable RLB when RLB is disabled and locked regions present will result
           // with an ignored write
-          bins sticky = binsof(cp_rlb) intersect {1} && binsof(cp_wdata_rlb) intersect {0}
+          bins sticky = binsof(cp_rlb) intersect {0} && binsof(cp_wdata_rlb) intersect {1}
             iff (cs_registers_i.g_pmp_registers.any_pmp_entry_locked);
       }
 
@@ -640,16 +639,26 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
         ignore_bins unsupported_priv_lvl =
           binsof(cs_registers_i.mstatus_q.mpp) intersect {PRIV_LVL_H, PRIV_LVL_S} ||
           binsof(cs_registers_i.priv_mode_id_o) intersect {PRIV_LVL_H, PRIV_LVL_S};
+
+        // Cannot have mprv set in U mode (as it is cleared when executing an `mret` which takes the
+        // hart into U mode).
+        illegal_bins no_mrpv_in_umode =
+          binsof(cs_registers_i.priv_mode_id_o) intersect {PRIV_LVL_U};
       }
 
-      pmp_instr_edge_cross: cross if_stage_i.instr_is_compressed_id_o,
+      pmp_instr_edge_cross: cross if_stage_i.instr_is_compressed_out,
                                   pmp_iside_req_err, pmp_iside2_req_err
-                              iff (pmp_iside_boundary_cross);
+                              iff (pmp_iside_boundary_cross) {
+        // Compressed instruction cannot see an error over the boundary as it only ever does
+        // a single 16-bit fetch.
+        illegal_bins no_iside2_err_on_compressed =
+          binsof(if_stage_i.instr_is_compressed_out) intersect {1'b1} &&
+          binsof(pmp_iside2_req_err) intersect {1'b1};
+      }
 
       misaligned_lsu_access_cross: cross misaligned_pmp_err_last,
-                                         load_store_unit_i.fcov_ls_mis_pmp_err_2,
-                                         pmp_dside_boundary_cross;
-
+                                         load_store_unit_i.fcov_ls_mis_pmp_err_2
+                                   iff (pmp_dside_boundary_cross);
     endgroup
 
     `DV_FCOV_INSTANTIATE_CG(pmp_top_cg, en_pmp_fcov)

diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv
@@ -596,7 +596,7 @@ module ibex_load_store_unit #(
   `DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
   `DV_FCOV_SIGNAL(logic, ls_first_req, lsu_req_i & (ls_fsm_cs == IDLE))
   `DV_FCOV_SIGNAL(logic, ls_second_req,
-    (ls_fsm_cs inside {WAIT_GNT, WAIT_RVALID_MIS}) & data_req_o & addr_incr_req_o)
+    (ls_fsm_cs inside {WAIT_RVALID_MIS}) & data_req_o & addr_incr_req_o)
   `DV_FCOV_SIGNAL(logic, ls_mis_pmp_err_1,
     (ls_fsm_cs inside {WAIT_RVALID_MIS, WAIT_GNT_MIS}) && pmp_err_q)
   `DV_FCOV_SIGNAL(logic, ls_mis_pmp_err_2,