Email: iamwangfw@126.com

秋招数字IC岗---常考的设计题：

The-project-of-Verilog

sync_fifo ver1 in verilog and their testbench.
sync_fifo ver2 in verilog and their testbench.
async fifo ver1 in verilog and it's testbench.
mod3
The communication by the way of Shake_hand:send part
The communication by the way of Shake_hand:receive part
The top level of hand_shake consiting of 5&6's codes
Random number generator
IIC communication module
8 bits adder based on two stages pipeline
8 bits adder based on four states pipeline
System verilog used to design testbench
RNG test by system verilog testbench
ALU module and it's testbench of system verilog
A memory working in stack
A simple module used to convert binary code to gray code
A special number finder in memory
FSM of drink machines
DMUX used to data bits synchronization
A module used to extend the width of the pulse
A auto drink machine
Div odd
Sequency detector
Sync FIFO practice
FIFO
Asynchronous Reset Synchronous Release
Generation a list of numbers
Auto drink machine
key scan
AXI_handshake
AXI handshake process
SEQ detector with FSM
Mod3
level to pluse
fast to slow clock domain

36 && 37. DIV 3 with 2 methods

Clk div 5
Clk div even
fifo
serial to para
clock change
async clocks change
Edge det
Cycle cnt
Gray to bin
PWM driver