Email: iamwangfw@126.com
秋招数字IC岗---常考的设计题：
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sync_fifo ver1 in verilog and their testbench.
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sync_fifo ver2 in verilog and their testbench.
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async fifo ver1 in verilog and it's testbench.
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mod3
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The communication by the way of Shake_hand:send part
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The communication by the way of Shake_hand:receive part
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The top level of hand_shake consiting of 5&6's codes
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Random number generator
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IIC communication module
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8 bits adder based on two stages pipeline
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8 bits adder based on four states pipeline
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System verilog used to design testbench
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RNG test by system verilog testbench
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ALU module and it's testbench of system verilog
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A memory working in stack
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A simple module used to convert binary code to gray code
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A special number finder in memory
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FSM of drink machines
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DMUX used to data bits synchronization
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A module used to extend the width of the pulse
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A auto drink machine
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Div odd
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Sequency detector
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Sync FIFO practice
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FIFO
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Asynchronous Reset Synchronous Release
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Generation a list of numbers
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Auto drink machine
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key scan
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AXI_handshake
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AXI handshake process
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SEQ detector with FSM
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Mod3
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level to pluse
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fast to slow clock domain
36 && 37. DIV 3 with 2 methods
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Clk div 5
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Clk div even
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fifo
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serial to para
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clock change
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async clocks change
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Edge det
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Cycle cnt
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Gray to bin
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PWM driver