GitHub - marius-verdier/cpu_vhdl: Construction of a micro processor type RISC using VHDL

marius-verdier / cpu_vhdl Public

Construction of a micro processor type RISC using VHDL

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Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
db		db
output_files		output_files
simulation/modelsim		simulation/modelsim
ALU.vhd		ALU.vhd
CPU.bdf		CPU.bdf
CPU.qpf		CPU.qpf
CPU.qsf		CPU.qsf
CPU.qws		CPU.qws
CPU.sdc		CPU.sdc
CPU.vhd		CPU.vhd
CPU.vhd.bak		CPU.vhd.bak
CPU_assignment_defaults.qdf		CPU_assignment_defaults.qdf
CPU_nativelink_simulation.rpt		CPU_nativelink_simulation.rpt
Event_Detect.bsf		Event_Detect.bsf
Event_Detect.vhd		Event_Detect.vhd
Fetch.vhd		Fetch.vhd
Ram.vhd		Ram.vhd
Rom.vhd		Rom.vhd
SEG7_LUT.bsf		SEG7_LUT.bsf
SEG7_LUT.cmp		SEG7_LUT.cmp
SEG7_LUT.vhd		SEG7_LUT.vhd
dig2dec.bsf		dig2dec.bsf
dig2dec.cmp		dig2dec.cmp
dig2dec.vhd		dig2dec.vhd
instruction_decoder.vhd		instruction_decoder.vhd
ram.bsf		ram.bsf
reg.vhd		reg.vhd
register_file.vhd		register_file.vhd
rom.bsf		rom.bsf