(c)2018 Miguel Angel Rodriguez Jodar. See LICENSE for licensing details.
A SPI master interface core for CPLD/FPGA written in Verilog. Testbench, using a small SPI slave core, is included.
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A SPI master interface core for CPLD/FPGA
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mcleod-ideafix/spi_master
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A SPI master interface core for CPLD/FPGA
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