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Code coverage : Add option to support coverage condition with arithme…
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…tic operations (#2694)

Fix issue#1902
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AyoubJalali authored Jan 8, 2025
1 parent e55f25d commit 6268d28
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion verif/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -214,7 +214,7 @@ ALL_UVM_FLAGS = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \
$(VCS_HOME)/etc/uvm/src/uvm_pkg.sv -ntb_opts uvm-1.2 -timescale=1ns/1ps \
-assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \
$(if $(DEBUG), -debug_access+all $(if $(VERDI), -kdb) $(if $(TRACE_COMPACT),+vcs+fsdbon)) \
-cm_seqnoconst -diag noconst \
-cm_seqnoconst -diag noconst -cm_cond arith \

ALL_SIMV_UVM_FLAGS = +vcs+lic+wait $(issrun_opts) \

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