Add RISCV documentation for cv64a6_mmu (#2315)

docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html

@@ -3328,7 +3328,10 @@ <h5 id="privstack">3.1.6.1. Privilege and Global Interrupt-Enable Stack in <code
 </div>
 <div class="sect4">
 <h5 id="machine-double-trap">3.1.6.2. Double Trap Control in <code>mstatus</code> Register</h5>
-
+<div class="paragraph">
+<p>[CV32A65X] As Double Trap Control (Smdbltrp extension) is not implemented,
+MDT field is read-only 0.</p>
+</div>
 </div>
 <div class="sect4">
 <h5 id="xlen-control">3.1.6.3. Base ISA Control in <code>mstatus</code> Register</h5>
@@ -3363,7 +3366,10 @@ <h5 id="_endianness_control_in_mstatus_and_mstatush_registers">3.1.6.5. Endianne
 <p>It is always little-endian in M-Mode, the MBE is read-only zero.</p>
 </div>
 <div class="paragraph">
-<p>U-Mode and S-Mode are not implemented, UBE and SBE are read-only 0.</p>
+<p>S-Mode is not implemented, SBE is read-only 0.</p>
+</div>
+<div class="paragraph">
+<p>U-Mode is not implemented, UBE is read-only 0.</p>
 </div>
 </div>
 <div class="sect4">
@@ -3638,8 +3644,10 @@ <h4 id="_hardware_performance_monitor">3.1.10. Hardware Performance Monitor</h4>
 CSRs return bits 31-0 of the corresponding register, and writes change
 only bits 31-0; reads of the <code>mcycleh</code>, <code>minstreth</code>, and <code>mhpmcounter<em>n</em>h</code>
 CSRs return bits 63-32 of the corresponding register, and writes change
-only bits 63-32.
-As the Sscofpmf extension is not implemented, the <code>mhpmevent<em>n</em>h</code> CSRs
+only bits 63-32.</p>
+</div>
+<div class="paragraph">
+<p>As the Sscofpmf extension is not implemented, the <code>mhpmevent<em>n</em>h</code> CSRs
 are not provided.</p>
 </div>
 </div>
@@ -3995,7 +4003,7 @@ <h4 id="sec:menvcfg">3.1.18. Machine Environment Configuration (<code>menvcfg</c
 privileged than M.</p>
 </div>
 <div class="paragraph">
-<p>As XLEN=32, <code>menvcfgh</code> is a 32-bit read/write register
+<p>[CV32A65X] As XLEN=32, <code>menvcfgh</code> is a 32-bit read/write register
 that aliases bits 63:32 of <code>menvcfg</code>.</p>
 </div>
 <div class="paragraph">
@@ -4062,10 +4070,6 @@ <h4 id="_machine_timer_mtime_and_mtimecmp_registers">3.2.1. Machine Timer (<code
 value without spuriously generating a timer interrupt due to the
 intermediate value of the comparand:</p>
 </div>
-<div class="paragraph">
-<p>For RV64, naturally aligned 64-bit memory accesses to the <code>mtime</code> and
-<code>mtimecmp</code> registers are additionally supported and are atomic.</p>
-</div>
 <div class="literalblock">
 <div class="title">Sample code for setting the 64-bit time comparand in RV32 assuming a little-endian memory system and that the registers live in a strongly ordered I/O region.  Storing -1 to the low-order bits of <code>mtimecmp</code> prevents <code>mtimecmp</code> from temporarily becoming smaller than the lesser of the old and new values.</div>
 <div class="content">

docs/06_cv64a6_mmu/index.rst

@@ -0,0 +1,8 @@
+CV32A65X documentation
+======================
+
+.. toctree::
+   :maxdepth: 1
+
+   riscv/unpriv.rst
+   riscv/priv.rst

docs/06_cv64a6_mmu/riscv/Makefile

@@ -0,0 +1,10 @@
+#   Copyright 2024 Thales DIS France SAS
+#   Licensed under the Solderpad Hardware License, Version 2.1 (the "License");
+#   you may not use this file except in compliance with the License.
+#   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#   You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+#   Original Author: Thales DIS
+
+CONFIG := cv64a6_mmu
+include ../../riscv-isa/build.mk

docs/06_cv64a6_mmu/riscv/priv.rst

@@ -0,0 +1,14 @@
+..
+   Copyright (c) 2024 Thales
+   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: Jean-Roch COULON - Thales
+
+Privileged RISC-V ISA
+=====================
+
+.. raw:: html
+   :file: priv-isa-cv64a6_mmu.html

docs/06_cv64a6_mmu/riscv/src/config.adoc

@@ -0,0 +1,23 @@
+:ohg-config: CV64A6_MMU
+:XLEN: 64
+:RVA: false
+:RVC: true
+:RVS: true
+:RVU: true
+:RVH: false
+:SV: SV0
+:RVZicfilp: false
+:RVZicfiss: false
+:RVZsmstateen: false
+:RVZsmcsrind-RVZsscsrind: false
+:RVZsmepmp: false
+:RVZsmcntrpmf: false
+:RVZsmrnmi: false
+:RVZsmcdeleg: false
+:RVZsstc: false
+:RVZsscofpmf: false
+:RVZsmmpm: false
+:DCacheEn: false
+:MTvalEn: false
+:MTvecDirectEn: true
+:note: false

docs/06_cv64a6_mmu/riscv/unpriv.rst

@@ -0,0 +1,14 @@
+..
+   Copyright (c) 2024 Thales
+   Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+   You may obtain a copy of the License at https://solderpad.org/licenses/
+
+   Original Author: Jean-Roch COULON - Thales
+
+Unprivileged RISC-V ISA
+=======================
+
+.. raw:: html
+   :file: unpriv-isa-cv64a6_mmu.html

docs/riscv-isa/src/config_define.adoc

@@ -0,0 +1,68 @@
+
+ifeval::["{ohg-config}"=="CV32A65X"]
+:archi-CVA6:
+// specify that it is a custom architecture
+:archi-not-default:
+endif::[]
+
+ifeval::["{ohg-config}"=="CV64A6_MMU"]
+:archi-CVA6:
+// specify that it is a custom architecture
+:archi-not-default:
+endif::[]
+
+ifndef::archi-not-default[]
+:archi-default:
+endif::[]
+
+ifeval::[{RVS} == true]
+:RVS-true:
+endif::[]
+
+ifeval::[{RVU} == true]
+:RVU-true:
+endif::[]
+
+ifeval::[{XLEN} == 32]
+:XLEN-32:
+endif::[]
+
+ifeval::[{XLEN} == 64]
+:XLEN-64:
+endif::[]
+
+ifeval::[{RVZsmcntrpmf} == true]
+:RVZsmcntrpmf-true:
+endif::[]
+
+ifeval::[{RVC} == true]
+:RVC-true:
+endif::[]
+
+ifeval::[{MTvecDirectEn} == true]
+:MTvecDirectEn-true:
+endif::[]
+
+ifeval::[{MTvalEn} == true]
+:MTvalEn-true:
+endif::[]
+
+ifeval::[{RVZsmepmp} == true]
+:RVZsmepmp-true:
+endif::[]
+
+ifeval::[{DCacheEn} == true]
+:DCacheEn-true:
+endif::[]
+
+ifeval::[{RVA} == true]
+:RVA-true:
+endif::[]
+
+ifeval::[{RVZsmdbltrp} == true]
+:RVZsmdbltrp-true:
+endif::[]
+
+ifeval::[{RVZicfilp} == true]
+:RVZicfilp-true:
+endif::[]