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verible-verilog-format: apply it on core directory (#1668)
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using verible-v0.0-3430-g060bde0f/bin/verible-verilog-format
with default configuration

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
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@ASintzoff
ASintzoff authored Dec 4, 2023
1 parent 36c105a commit c51819d
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Showing 21 changed files with 325 additions and 243 deletions.
54 changes: 37 additions & 17 deletions core/alu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -87,11 +87,11 @@ module alu
endcase
end
unique case (fu_data_i.operation)
SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1;
SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2;
SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3;
CTZ: operand_a_bitmanip = operand_a_rev;
default: ;
SH1ADD: operand_a_bitmanip = fu_data_i.operand_a << 1;
SH2ADD: operand_a_bitmanip = fu_data_i.operand_a << 2;
SH3ADD: operand_a_bitmanip = fu_data_i.operand_a << 3;
CTZ: operand_a_bitmanip = operand_a_rev;
default: ;
endcase
end
end
Expand Down Expand Up @@ -228,11 +228,33 @@ module alu
end

if (ariane_pkg::BITMANIP) begin : gen_orcbw_rev8w_results
assign orcbw = {{8{|fu_data_i.operand_a[31:24]}}, {8{|fu_data_i.operand_a[23:16]}}, {8{|fu_data_i.operand_a[15:8]}}, {8{|fu_data_i.operand_a[7:0]}}};
assign rev8w = {{fu_data_i.operand_a[7:0]}, {fu_data_i.operand_a[15:8]}, {fu_data_i.operand_a[23:16]}, {fu_data_i.operand_a[31:24]}};
assign orcbw = {
{8{|fu_data_i.operand_a[31:24]}},
{8{|fu_data_i.operand_a[23:16]}},
{8{|fu_data_i.operand_a[15:8]}},
{8{|fu_data_i.operand_a[7:0]}}
};
assign rev8w = {
{fu_data_i.operand_a[7:0]},
{fu_data_i.operand_a[15:8]},
{fu_data_i.operand_a[23:16]},
{fu_data_i.operand_a[31:24]}
};
if (riscv::IS_XLEN64) begin : gen_64b
assign orcbw_result = {{8{|fu_data_i.operand_a[63:56]}}, {8{|fu_data_i.operand_a[55:48]}}, {8{|fu_data_i.operand_a[47:40]}}, {8{|fu_data_i.operand_a[39:32]}}, orcbw};
assign rev8w_result = {rev8w , {fu_data_i.operand_a[39:32]}, {fu_data_i.operand_a[47:40]}, {fu_data_i.operand_a[55:48]}, {fu_data_i.operand_a[63:56]}};
assign orcbw_result = {
{8{|fu_data_i.operand_a[63:56]}},
{8{|fu_data_i.operand_a[55:48]}},
{8{|fu_data_i.operand_a[47:40]}},
{8{|fu_data_i.operand_a[39:32]}},
orcbw
};
assign rev8w_result = {
rev8w,
{fu_data_i.operand_a[39:32]},
{fu_data_i.operand_a[47:40]},
{fu_data_i.operand_a[55:48]},
{fu_data_i.operand_a[63:56]}
};
end else begin : gen_32b
assign orcbw_result = orcbw;
assign rev8w_result = rev8w;
Expand All @@ -257,11 +279,10 @@ module alu
unique case (fu_data_i.operation)
// Standard Operations
ANDL, ANDN: result_o = fu_data_i.operand_a & operand_b_neg[riscv::XLEN:1];
ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[riscv::XLEN:1];
ORL, ORN: result_o = fu_data_i.operand_a | operand_b_neg[riscv::XLEN:1];
XORL, XNOR: result_o = fu_data_i.operand_a ^ operand_b_neg[riscv::XLEN:1];
// Adder Operations
ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD:
result_o = adder_result;
ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: result_o = adder_result;
// Shift Operations
SLL, SRL, SRA: result_o = (riscv::IS_XLEN64) ? shift_result : shift_result32;
// Comparison Operations
Expand All @@ -277,7 +298,8 @@ module alu
rorw = ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} >> fu_data_i.operand_b[4:0]) | ({{riscv::XLEN-32{1'b0}},fu_data_i.operand_a[31:0]} << (riscv::XLEN-32-fu_data_i.operand_b[4:0]));
if (riscv::IS_XLEN64) begin
unique case (fu_data_i.operation)
CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount}; // change
CLZW, CTZW:
result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN - 5{1'b0}}, lz_tz_wcount}; // change
ROLW: result_o = {{riscv::XLEN - 32{rolw[31]}}, rolw};
RORW, RORIW: result_o = {{riscv::XLEN - 32{rorw[31]}}, rorw};
default: ;
Expand Down Expand Up @@ -319,10 +341,8 @@ module alu
ROR, RORI:
result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));

ORCB:
result_o = orcbw_result;
REV8:
result_o = rev8w_result;
ORCB: result_o = orcbw_result;
REV8: result_o = rev8w_result;

default: ; // default case to suppress unique warning
endcase
Expand Down
53 changes: 26 additions & 27 deletions core/axi_shim.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -84,36 +84,36 @@ module axi_shim #(
logic [AddrIndex-1:0] wr_cnt_d, wr_cnt_q;
logic wr_single_req, wr_cnt_done, wr_cnt_clr, wr_cnt_en;

assign wr_single_req = (wr_blen_i == 0);
assign wr_single_req = (wr_blen_i == 0);

// address
assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction
assign axi_req_o.aw.addr = wr_addr_i[CVA6Cfg.AxiAddrWidth-1:0];
assign axi_req_o.aw.size = wr_size_i;
assign axi_req_o.aw.len = wr_blen_i;
assign axi_req_o.aw.id = wr_id_i;
assign axi_req_o.aw.prot = 3'b0;
assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; // Use BURST_INCR for AXI regular transaction
assign axi_req_o.aw.addr = wr_addr_i[CVA6Cfg.AxiAddrWidth-1:0];
assign axi_req_o.aw.size = wr_size_i;
assign axi_req_o.aw.len = wr_blen_i;
assign axi_req_o.aw.id = wr_id_i;
assign axi_req_o.aw.prot = 3'b0;
assign axi_req_o.aw.region = 4'b0;
assign axi_req_o.aw.lock = wr_lock_i;
assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE;
assign axi_req_o.aw.qos = 4'b0;
assign axi_req_o.aw.atop = wr_atop_i;
assign axi_req_o.aw.user = '0;
assign axi_req_o.aw.lock = wr_lock_i;
assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE;
assign axi_req_o.aw.qos = 4'b0;
assign axi_req_o.aw.atop = wr_atop_i;
assign axi_req_o.aw.user = '0;

// data
assign axi_req_o.w.data = wr_data_i[wr_cnt_q];
assign axi_req_o.w.user = wr_user_i[wr_cnt_q];
assign axi_req_o.w.strb = wr_be_i[wr_cnt_q];
assign axi_req_o.w.last = wr_cnt_done;
assign axi_req_o.w.data = wr_data_i[wr_cnt_q];
assign axi_req_o.w.user = wr_user_i[wr_cnt_q];
assign axi_req_o.w.strb = wr_be_i[wr_cnt_q];
assign axi_req_o.w.last = wr_cnt_done;

// write response
assign wr_exokay_o = (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY);
assign axi_req_o.b_ready = wr_rdy_i;
assign wr_valid_o = axi_resp_i.b_valid;
assign wr_id_o = axi_resp_i.b.id;
assign wr_exokay_o = (axi_resp_i.b.resp == axi_pkg::RESP_EXOKAY);
assign axi_req_o.b_ready = wr_rdy_i;
assign wr_valid_o = axi_resp_i.b_valid;
assign wr_id_o = axi_resp_i.b.id;

// tx counter
assign wr_cnt_done = (wr_cnt_q == wr_blen_i);
assign wr_cnt_done = (wr_cnt_q == wr_blen_i);
assign wr_cnt_d = (wr_cnt_clr) ? '0 : (wr_cnt_en && CVA6Cfg.AxiBurstWriteEn) ? wr_cnt_q + 1 : wr_cnt_q;

always_comb begin : p_axi_write_fsm
Expand Down Expand Up @@ -149,7 +149,7 @@ module axi_shim #(
default: wr_state_d = IDLE;
endcase
// its a request for the whole cache line
end else if(CVA6Cfg.AxiBurstWriteEn) begin
end else if (CVA6Cfg.AxiBurstWriteEn) begin
wr_cnt_en = axi_resp_i.w_ready;

case ({
Expand Down Expand Up @@ -193,7 +193,7 @@ module axi_shim #(
default: begin
///////////////////////////////////
// ~> we need to wait for an aw_ready and there is at least one outstanding write
if(CVA6Cfg.AxiBurstWriteEn) begin
if (CVA6Cfg.AxiBurstWriteEn) begin
if (wr_state_q == WAIT_LAST_W_READY_AW_READY) begin
axi_req_o.w_valid = 1'b1;
axi_req_o.aw_valid = 1'b1;
Expand Down Expand Up @@ -227,12 +227,11 @@ module axi_shim #(
end
default: ;
endcase
end
///////////////////////////////////
// ~> all data has already been sent, we are only waiting for the aw_ready
end ///////////////////////////////////
// ~> all data has already been sent, we are only waiting for the aw_ready
else if (wr_state_q == WAIT_AW_READY_BURST) begin
axi_req_o.aw_valid = 1'b1;

if (axi_resp_i.aw_ready) begin
wr_state_d = IDLE;
wr_gnt_o = 1'b1;
Expand Down
10 changes: 7 additions & 3 deletions core/cache_subsystem/axi_adapter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,11 @@ module axi_adapter #(
DATA_WIDTH / CVA6Cfg.AxiDataWidth
) : 1;
localparam MAX_OUTSTANDING_AW = CVA6Cfg.MaxOutstandingStores;
localparam MAX_OUTSTANDING_AW_CNT_WIDTH = $clog2(MAX_OUTSTANDING_AW + 1) > 0 ? $clog2(MAX_OUTSTANDING_AW + 1) : 1;
localparam MAX_OUTSTANDING_AW_CNT_WIDTH = $clog2(
MAX_OUTSTANDING_AW + 1
) > 0 ? $clog2(
MAX_OUTSTANDING_AW + 1
) : 1;

typedef logic [MAX_OUTSTANDING_AW_CNT_WIDTH-1:0] outstanding_aw_cnt_t;

Expand Down Expand Up @@ -369,8 +373,8 @@ module axi_adapter #(
end
end
end
// if the request was not an atomic we can possibly issue
// other requests while waiting for the response
// if the request was not an atomic we can possibly issue
// other requests while waiting for the response
end else begin
if ((amo_q == ariane_pkg::AMO_NONE) && (outstanding_aw_cnt_q != MAX_OUTSTANDING_AW)) begin
state_d = IDLE;
Expand Down
4 changes: 3 additions & 1 deletion core/cache_subsystem/cva6_icache.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,9 @@ module cva6_icache
// main control logic
///////////////////////////////////////////////////////
logic addr_ni;
assign addr_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, {{64-riscv::PLEN{1'b0}}, areq_i.fetch_paddr});
assign addr_ni = config_pkg::is_inside_nonidempotent_regions(
CVA6Cfg, {{64 - riscv::PLEN{1'b0}}, areq_i.fetch_paddr}
);
always_comb begin : p_fsm
// default assignment
state_d = state_q;
Expand Down
6 changes: 5 additions & 1 deletion core/cache_subsystem/miss_handler.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -689,7 +689,11 @@ module axi_adapter_arbiter #(
input rsp_t rsp_i
);

localparam MAX_OUTSTANDING_CNT_WIDTH = $clog2(MAX_OUTSTANDING_REQ + 1) > 0 ? $clog2(MAX_OUTSTANDING_REQ + 1) : 1;
localparam MAX_OUTSTANDING_CNT_WIDTH = $clog2(
MAX_OUTSTANDING_REQ + 1
) > 0 ? $clog2(
MAX_OUTSTANDING_REQ + 1
) : 1;

typedef logic [MAX_OUTSTANDING_CNT_WIDTH-1:0] outstanding_cnt_t;

Expand Down
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