Bump CVV 2465 and adapt cva6pkg (#2263)

openhwgroup · Jun 17, 2024 · c78ede9 · c78ede9
1 parent c93587b
commit c78ede9
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Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/verif/core-v-verif b/verif/core-v-verif
diff --git a/verif/tb/core/uvma_cva6pkg_utils.sv b/verif/tb/core/uvma_cva6pkg_utils.sv
@@ -36,7 +36,7 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
     cfg.ext_zcb_supported = CVA6Cfg.RVZCB;
     cfg.ext_zifencei_supported = 1;
     cfg.ext_zicsr_supported = 1;
-    cfg.ext_zicntr_supported = 1;
+    cfg.ext_zicntr_supported = 0;
 
     cfg.ext_cv32a60x_supported = 1;
 
@@ -71,8 +71,9 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
     void'(spike_set_param_uint64_t(base, "mtvec_vectored_alignment", 64 * 4));
     void'(spike_set_param_str(base, "extensions", "cv32a60x"));
 
-    void'(spike_set_param_bool(base, "status_xs_field_we_enable", 1'b1));
-    void'(spike_set_param_bool(base, "status_xs_field_we", 1'b0));
+    // All enabled except XS and TW bits
+    void'(spike_set_param_uint64_t(base, "mstatus_write_mask", 'hFDFE_7FFF));
+
     void'(spike_set_param_uint64_t(base, "misa_override_value", get_misa(cfg)));
     void'(spike_set_param_uint64_t(base, "misa_override_mask", 64'h0FFF_FFFF));
     void'(spike_set_param_bool    (base, "misa_we_enable", 1'b1));
+1 −1		lib/uvm_agents/uvma_rvfi/seq/uvma_rvfi_instr_seq_item.sv
+1 −0		lib/uvm_agents/uvma_rvfi/uvma_rvfi_constants.sv
+1 −1		lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_if.sv
+17 −24		lib/uvm_components/uvmc_rvfi_scoreboard/uvmc_rvfi_scoreboard_utils.sv
+410 −0		vendor/patches/riscv/riscv-isa-sim/0025-debug-infra.patch
+121 −85		vendor/riscv/riscv-isa-sim/riscv/Proc.cc
+11 −1		vendor/riscv/riscv-isa-sim/riscv/Proc.h
+1 −0		vendor/riscv/riscv-isa-sim/riscv/execute.cc
+1 −1		vendor/riscv/riscv-isa-sim/riscv/processor.h