Connect CSRs info from RVFI_CSR in the testbench & update simulation …

…target (#1879)
openhwgroup · Feb 28, 2024 · ce0ab81 · ce0ab81
1 parent 5dceb0d
commit ce0ab81
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Showing 9 changed files with 215 additions and 58 deletions.
diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv
@@ -167,7 +167,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
          clknrst_cfg.enabled   == 1;
          isacov_cfg.enabled    == 1;
          rvfi_cfg.enabled      == 1;
-         rvfi_cfg.csr_enabled  == 0;
+         rvfi_cfg.csr_enabled  == 1;
       }
 
       isacov_cfg.seq_instr_group_x2_enabled == 1;

diff --git a/verif/regress/dv-csr-embedded-tests.sh b/verif/regress/dv-csr-embedded-tests.sh
@@ -23,7 +23,7 @@ source ./verif/sim/setup-env.sh
 export cov=1 #enable the Code Coverage
 
 if ! [ -n "$DV_TARGET" ]; then
-  DV_TARGET=cv32a6_embedded
+  DV_TARGET=cv32a65x
 fi
 
 if ! [ -n "$DV_SIMULATORS" ]; then

diff --git a/verif/regress/dv-generated-tests.sh b/verif/regress/dv-generated-tests.sh
@@ -24,7 +24,7 @@ source ./verif/regress/install-spike.sh
 source ./verif/sim/setup-env.sh
 
 if ! [ -n "$DV_TARGET" ]; then
-  DV_TARGET=cv32a6_embedded
+  DV_TARGET=cv32a65x
 fi
 
 if ! [ -n "$DV_SIMULATORS" ]; then

diff --git a/verif/regress/dv-generated-xif-tests.sh b/verif/regress/dv-generated-xif-tests.sh
@@ -24,7 +24,7 @@ source ./verif/regress/install-spike.sh
 source ./verif/sim/setup-env.sh
 
 if ! [ -n "$DV_TARGET" ]; then
-  DV_TARGET=cv32a6_embedded
+  DV_TARGET=cv32a65x
 fi
 
 if ! [ -n "$DV_SIMULATORS" ]; then

diff --git a/verif/sim/cov-exclude-mod.lst b/verif/sim/cov-exclude-mod.lst
@@ -11,3 +11,4 @@
 -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.instr_tracer_i
 -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.tracer_if
 -tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.genblk6.i_cva6_rvfi_combi
+-tree uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.i_cva6_rvfi_probes
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
@@ -464,7 +464,7 @@ def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, outp
     base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv)
     cmd = get_iss_cmd(base_cmd, elf, target, log)
     logging.info("[%0s] Running ISS simulation: %s" % (iss, cmd))
-    run_cmd(cmd, 300, debug_cmd = debug_cmd)
+    run_cmd(cmd, 500, debug_cmd = debug_cmd)
     logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf))
   if len(iss_list) == 2:
     compare_iss_log(iss_list, log_list, report)

diff --git a/verif/tb/uvmt/uvmt_cva6_macros.sv b/verif/tb/uvmt/uvmt_cva6_macros.sv
@@ -19,5 +19,34 @@
 `ifndef __UVMT_CVA6_MACROS_SV__
 `define __UVMT_CVA6_MACROS_SV__
 
+// Assign for RVFI CSR interface
+`define RVFI_CSR_ASSIGN(csr_name) \
+      uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN)  rvfi_csr_``csr_name``_if [RVFI_NRET-1:0](); \
+   for (genvar i = 0; i < RVFI_NRET; i++) begin \
+      assign  rvfi_csr_``csr_name``_if[i].clk              = clknrst_if.clk; \
+      assign  rvfi_csr_``csr_name``_if[i].reset_n          = clknrst_if.reset_n; \
+      assign  rvfi_csr_``csr_name``_if[i].rvfi_csr_rmask   = rvfi_if.rvfi_csr_o.``csr_name``.rmask; \
+      assign  rvfi_csr_``csr_name``_if[i].rvfi_csr_wmask   = rvfi_if.rvfi_csr_o.``csr_name``.wmask; \
+      assign  rvfi_csr_``csr_name``_if[i].rvfi_csr_rdata   = rvfi_if.rvfi_csr_o.``csr_name``.rdata; \
+      assign  rvfi_csr_``csr_name``_if[i].rvfi_csr_wdata   = rvfi_if.rvfi_csr_o.``csr_name``.wdata; \
+   end \
+
+`define RVFI_CSR_SUFFIX_ASSIGN(csr_name, idx) \
+      uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN)  rvfi_csr_``csr_name````idx``_if [RVFI_NRET-1:0](); \
+   for (genvar i = 0; i < RVFI_NRET; i++) begin \
+      assign  rvfi_csr_``csr_name````idx``_if[i].clk              = clknrst_if.clk; \
+      assign  rvfi_csr_``csr_name````idx``_if[i].reset_n          = clknrst_if.reset_n; \
+      assign  rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rmask   = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rmask; \
+      assign  rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wmask   = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wmask; \
+      assign  rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rdata   = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rdata; \
+      assign  rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wdata   = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wdata; \
+   end \
+
+// Create uvm_config_db::set call for a CSR interface
+`define RVFI_CSR_UVM_CONFIG_DB_SET(csr_name, idx) \
+  uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \
+                                                .inst_name("*"), \
+                                                .field_name({"csr_", `"csr_name`", "_vif", $sformatf("%0d", ``idx``)}), \
+                                                .value(rvfi_csr_``csr_name``_if[``idx``])); \
 
 `endif // __UVMT_CVA6_MACROS_SV__
diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv
diff --git a/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv b/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv
@@ -26,6 +26,7 @@ interface uvmt_rvfi_if #(
                     parameter type rvfi_instr_t = logic
 ) (
                     output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o,
+                    output ariane_pkg::rvfi_csr_t rvfi_csr_o,
                     output logic[31:0] tb_exit_o
                                  );