Add missing datatype to the rvfi_mem_paddr port

openhwgroup · Jan 8, 2025 · fbec8ef · fbec8ef
1 parent 50243f8
commit fbec8ef
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Showing 4 changed files with 4 additions and 8 deletions.
diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv
@@ -155,7 +155,7 @@ module load_store_unit
     // RVFI inforamtion - RVFI
     output lsu_ctrl_t                    rvfi_lsu_ctrl_o,
     // RVFI information - RVFI
-    output            [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o
+    output logic      [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o
 );
 
   // data is misaligned

diff --git a/core/store_buffer.sv b/core/store_buffer.sv
@@ -150,11 +150,7 @@ module store_buffer
   assign req_port_o.data_be = commit_queue_q[commit_read_pointer_q].be;
   assign req_port_o.data_size = commit_queue_q[commit_read_pointer_q].data_size;
 
-  always_ff @(posedge clk_i) begin : rvfi_mem_paddr_ff
-    if (commit_i) begin
-      rvfi_mem_paddr_o <= speculative_queue_q[speculative_read_pointer_q].address;
-    end
-  end
+  assign rvfi_mem_paddr_o = speculative_queue_q[speculative_read_pointer_q].address;
 
   always_comb begin : store_if
     automatic logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt;

diff --git a/core/store_unit.sv b/core/store_unit.sv
@@ -59,7 +59,7 @@ module store_unit
     // Virtual address - TO_BE_COMPLETED
     output logic [CVA6Cfg.VLEN-1:0] vaddr_o,
     // RVFI information - RVFI
-    output [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o,
+    output logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr_o,
     // Transformed trap instruction out - TO_BE_COMPLETED
     output logic [31:0] tinst_o,
     // TO_BE_COMPLETED - TO_BE_COMPLETED

diff --git a/verif/core-v-verif b/verif/core-v-verif
+1 −1		MergeTest.md
+27 −40		lib/cv_dv_utils/uvm/Files.f
+3 −0		lib/cv_dv_utils/uvm/bp_gen/bp_vif.sv
+8 −11		lib/cv_dv_utils/uvm/clock_gen/clock_driver_c.svh
+3 −0		lib/cv_dv_utils/uvm/clock_mon/xrtl_clock_mon_vif.sv
+4 −0		lib/cv_dv_utils/uvm/memory_rsp_model/memory_response_if.sv
+18 −31		lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_agent.sv
+33 −34		lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_amo_synchronizer.sv
+45 −581		lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_drv.sv
+44 −518		lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_mon.sv
+14 −69		lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_synchronizer.sv
+4 −295		lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_vsqr.sv
+5 −158		lib/uvm_agents/uvma_axi5/src/obj/uvma_axi_cfg.sv
+0 −1		lib/uvm_agents/uvma_axi5/src/obj/uvma_axi_cntxt.sv
+0 −7		lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_base_seq.sv
+0 −978		lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_mst_seq.svh
+32 −53		lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_slv_seq.sv
+27 −77		lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_transaction.sv
+0 −124		lib/uvm_agents/uvma_axi5/src/uvma_axi_intf.sv
+0 −1		lib/uvm_agents/uvma_axi5/src/uvma_axi_pkg.sv
+137 −40		lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_cov_model.sv
+188 −241		lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_drv.sv
+134 −143		lib/uvm_agents/uvma_cvxif/src/comps/uvma_cvxif_mon.sv
+41 −46		lib/uvm_agents/uvma_cvxif/src/obj/uvma_cvxif_cfg.sv
+0 −3		lib/uvm_agents/uvma_cvxif/src/obj/uvma_cvxif_cntxt.sv
+7 −10		lib/uvm_agents/uvma_cvxif/src/seq/uvma_cvxif_req_item.sv
+5 −11		lib/uvm_agents/uvma_cvxif/src/seq/uvma_cvxif_resp_item.sv
+136 −141		lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_assert.sv
+11 −31		lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_intf.sv
+17 −70		lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_macros.sv
+2 −13		lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_pkg.sv
+45 −49		lib/uvm_agents/uvma_cvxif/src/uvma_cvxif_tdefs.sv
+0 −45		vendor/patches/riscv/riscv-isa-sim/0035-increase-pmp-granularity-to-8.patch
+0 −13		vendor/riscv/riscv-isa-sim/riscv/Proc.cc
+1 −2		vendor/riscv/riscv-isa-sim/riscv/processor.cc