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Merge branch 'riscv:master' into tariqkurd-repo/master
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tariqkurd-repo authored Jun 4, 2024
2 parents 29a9ab4 + 5181d13 commit d2beb46
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6 changes: 3 additions & 3 deletions parse.py
Original file line number Diff line number Diff line change
Expand Up @@ -193,9 +193,9 @@ def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]):
instruction is not added twice to the overall dictionary.
In the second pass, this function parses only pseudo_ops. For each pseudo_op
this function checks if the dependent extension and instruction, both, exit
before parsing it. The pseudo op is only added to the overall dictionary is
the dependent instruction is not present in the dictionary, else its
this function checks if the dependent extension and instruction, both, exist
before parsing it. The pseudo op is only added to the overall dictionary if
the dependent instruction is not present in the dictionary, else it is
skipped.
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2 changes: 1 addition & 1 deletion rv_v
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27
vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27
vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27

# Unit-stride F31..29=0ault-Only-First Loads
# Unit-stride Fault-Only-First Loads
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads
vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07
vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07
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