riscv32

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

cmake cpu pipeline cpp riscv gtest computer-architecture speculation branch-prediction riscv32 riscv-simulator riscv-emulator tomasulo-algorithm

Updated Jul 2, 2020
C++

franzflasch / riscv_em

Star

Simple risc-v emulator, able to run linux, written in C.

c linux emulator embedded-systems riscv risc-v embedded-c uclinux riscv32 riscv-linux rv32 riscv64 riscv-emulator risc-v64 rv64 riscv-em risc-v-emulator

Updated Apr 11, 2024
C

drom / awesome-riscv

Star

😎 A curated list of awesome RISC-V implementations

awesome riscv awesome-list hacktoberfest risc-v riscv32 riscv64

Updated Mar 12, 2023

dpretet / axi-crossbar

Sponsor

Star

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated Nov 26, 2024
SystemVerilog

jasonlin316 / RISC-V-CPU

Star

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

processor vector verilog chip risc-v riscv32 gate-level place-and-route tape-out

Updated Dec 2, 2019
Verilog

inpyjama / c-ninja-listings

Star

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

c makefile assembly-language risc-v baremetal riscv32 linker-script

Updated Oct 23, 2024
Makefile

svenssonjoel / lispBM

Star

An interpreter for a concurrent lisp with message-passing and pattern-matching.

language programming-language microcontroller lisp interpreter functional-programming pattern-matching esp32 repl concurrency freertos stm32f4 chibios zephyr nrf52 riscv32 quasiquotation

Updated Dec 30, 2024
C

splinedrive / lets_build_a_compiler_for_riscv

Star

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

c computer-science tutorial compiler spike riscv fpga-soc compiler-construction riscv32 riscv-sim riscv-asm crenshaw riscv-assembly

Updated Sep 26, 2022
C

ultraembedded / exactstep

Sponsor

Star

Instruction set simulator for RISC-V, MIPS and ARM-v6m

mips armv6 risc-v instruction-set-simulator mips32 riscv32 riscv64 riscv-simulator

Updated Sep 18, 2021
C++

tommythorn / yarvi

Star

Yet Another RISC-V Implementation

fpga riscv verilog fpga-soc risc-v riscv32

Updated Sep 21, 2024
Roff

risc0 / risc0-lean4

Star

A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover

riscv lean risc-v zero-knowledge riscv32 riscv32im lean4 zkvm risc0 zk-stark

Updated Feb 14, 2023
Lean

OpenMachine-ai / tinyfive

Star

TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples

machine-learning ai compiler assembly assembler ml riscv risc-v riscv32 riscv-asm riscv-simulator riscv-emulator riscv-assembly riscv-assembler risc-v-32-simulation risc-v-simulator

Updated Nov 1, 2023
Python

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riscv32

Here are 250 public repositories matching this topic...

LekKit / RVVM

chipsalliance / Cores-VeeR-EH1

sysprog21 / rv32emu

cahirwpz / mimiker

mrLSD / riscv-fs

tvlad1234 / pico-rv32ima

chipsalliance / Cores-VeeR-EL2

google / esh

skyzh / RISCV-Simulator

franzflasch / riscv_em

drom / awesome-riscv

dpretet / axi-crossbar

jasonlin316 / RISC-V-CPU

inpyjama / c-ninja-listings

svenssonjoel / lispBM

splinedrive / lets_build_a_compiler_for_riscv

ultraembedded / exactstep

tommythorn / yarvi

risc0 / risc0-lean4

OpenMachine-ai / tinyfive

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