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[Nvidia] Support fp8 to bf16 casting on RTX 4000 series #5544

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merged 2 commits into from
Jan 7, 2025
Merged

[Nvidia] Support fp8 to bf16 casting on RTX 4000 series #5544

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c154cec
Support fp8 to bf16 casting on RTX 4000 series
mbrookhart Jan 7, 2025
b5548fa
Merge branch 'main' into tests_on_4090
mbrookhart Jan 7, 2025
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49 changes: 35 additions & 14 deletions third_party/nvidia/lib/TritonNVIDIAGPUToLLVM/ElementwiseOpToLLVM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -190,19 +190,39 @@ static const Fp8ConversionDesc Fp16_to_Fp8E4M3Nv = {
"}",
32, 16, 2};

// Fp8E4M3 (x2) -> Fp16 (x2) (packed)
static const Fp8ConversionDesc Fp8E4M3Nv_to_Bf16 = {
"{ \n"
".reg .b32 a; \n"
".reg .f16 a<2>; \n"
".reg .b16 b<2>; \n"
"cvt.rn.f16x2.e4m3x2 a, $1; \n"
"mov.b32 {a0, a1}, a; \n"
"cvt.bf16.f16 b0, a0; \n"
"cvt.bf16.f16 b1, a1; \n"
"mov.b32 $0, {b0, b1}; \n"
"}",
16, 32, 2};
static const Fp8ConversionDesc Fp8E4M3Nv_to_Bf16(bool hasNativeFP) {
Fp8ConversionDesc ret;
// Fp8E4M3 (x2) -> Fp16 (x2) (packed)
if (!hasNativeFP) {
ret = {"{ \n"
".reg .b32 a; \n"
".reg .f16 a<2>; \n"
".reg .f32 b<2>; \n"
".reg .b16 c<2>; \n"
"cvt.rn.f16x2.e4m3x2 a, $1; \n"
"mov.b32 {a0, a1}, a; \n"
"cvt.f32.f16 b0, a0; \n"
"cvt.f32.f16 b1, a1; \n"
"cvt.rn.bf16.f32 c0, b0; \n"
"cvt.rn.bf16.f32 c1, b1; \n"
"mov.b32 $0, {c0, c1}; \n"
"}",
16, 32, 2};
} else {
ret = {"{ \n"
".reg .b32 a; \n"
".reg .f16 a<2>; \n"
".reg .b16 b<2>; \n"
"cvt.rn.f16x2.e4m3x2 a, $1; \n"
"mov.b32 {a0, a1}, a; \n"
"cvt.bf16.f16 b0, a0; \n"
"cvt.bf16.f16 b1, a1; \n"
"mov.b32 $0, {b0, b1}; \n"
"}",
16, 32, 2};
}
return ret;
}

// Bf16 (x2) -> Fp8E4M3 (x2) (packed)
static const Fp8ConversionDesc Bf16_to_Fp8E4M3Nv = {
Expand Down Expand Up @@ -424,7 +444,8 @@ struct FpToFpOpConversion
// F8 -> BF16
{{F8E5M2TyID, BF16TyID, undefRounding},
Fp8E5M2_to_Bf16(computeCapability >= 90)},
{{F8E4M3TyID, BF16TyID, undefRounding}, Fp8E4M3Nv_to_Bf16},
{{F8E4M3TyID, BF16TyID, undefRounding},
Fp8E4M3Nv_to_Bf16(computeCapability >= 90)},
// BF16 -> F8
{{BF16TyID, F8E5M2TyID, RoundingMode::RTNE},
Bf16_to_Fp8E5M2(computeCapability >= 90)},
Expand Down
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