Single-Cycle Processor

This is the VHDL implementation of a MIPS Single-Cycle Processor that I developed for the computer architecture course at my university. The processor is written entirely in VHDL and strictly "structural" in programming style i.e. no control flow (if/elsif/then/else etc.) or sequential statements. This processor fulfills a part of the MIPS instruction set architecture (ISA) and is able to perform arithmetic operations, logic comparison and operations, branch operations, register read/writes, memory read/writes, register-to-memory and memory-to-register operations.

This processor fulfills the following subset of the MIPS instruction set architecture:

arithmetic: add, addi, addu, sub, subu
logical: and, or, sll
data transfer: lw, sw
conditional branch: beq, bne, bgtz, slt, sltu

Deployment

This processor was tested and verified using ModelSim. We verify the functionality of the processor by feeding it binary MIPS instructions line-by-line and verify that all the operations are correctly interpreted, executed, and stored: cycle-by-cycle.

The top-level entity of the processor is "processor.vhd"

Built With

Notepad++ - Editor used for developing VHDL
ModelSim - Simulation tool for testing and verifying valid processor outputs

Acknowledgments

Course professor for project guidance
Course partners for co-development of the datapath

Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
EECS-361-Single-Processor		EECS-361-Single-Processor
IFU.vhd		IFU.vhd
README.md		README.md
and_5_to_1.vhd		and_5_to_1.vhd
and_8_to_1.vhd		and_8_to_1.vhd
and_gate.vhd		and_gate.vhd
and_gate_32.vhd		and_gate_32.vhd
and_gate_n.vhd		and_gate_n.vhd
and_n.vhd		and_n.vhd
bills_branch.dat		bills_branch.dat
dec_n.vhd		dec_n.vhd
dec_n_test.vhd		dec_n_test.vhd
decoder.vhd		decoder.vhd
decoder_tb.vhd		decoder_tb.vhd
dff.vhd		dff.vhd
dff_test.vhd		dff_test.vhd
dffr.vhd		dffr.vhd
dffr_a.vhd		dffr_a.vhd
dffr_a_test.vhd		dffr_a_test.vhd
dffr_test.vhd		dffr_test.vhd
eecs361.vhd		eecs361.vhd
eecs361_gates.vhd		eecs361_gates.vhd
extender.vhd		extender.vhd
extender_tb.vhd		extender_tb.vhd
fulladder_1.vhd		fulladder_1.vhd
fulladder_32.vhd		fulladder_32.vhd
input32_mux		input32_mux
mux.vhd		mux.vhd
mux_1_4.vhd		mux_1_4.vhd
mux_32.vhd		mux_32.vhd
mux_n.vhd		mux_n.vhd
mux_n_4.vhd		mux_n_4.vhd
mux_n_test.vhd		mux_n_test.vhd
nand_gate.vhd		nand_gate.vhd
nand_gate_32.vhd		nand_gate_32.vhd
nand_gate_n.vhd		nand_gate_n.vhd
nor_gate.vhd		nor_gate.vhd
nor_gate_32.vhd		nor_gate_32.vhd
nor_gate_n.vhd		nor_gate_n.vhd
not_gate.vhd		not_gate.vhd
not_gate_32.vhd		not_gate_32.vhd
not_gate_n.vhd		not_gate_n.vhd
old_components.vhd		old_components.vhd
or_gate.vhd		or_gate.vhd
or_gate_32.vhd		or_gate_32.vhd
or_gate_n.vhd		or_gate_n.vhd
or_n.vhd		or_n.vhd
processor.vhd		processor.vhd
register_32bit.vhd		register_32bit.vhd
register_32we		register_32we
register_component		register_component
register_file.vhd		register_file.vhd
sort_corrected_branch.dat		sort_corrected_branch.dat
sram.vhd		sram.vhd
sram_test.vhd		sram_test.vhd
syncram.vhd		syncram.vhd
unsigned_sum.dat		unsigned_sum.dat
xnor_gate.vhd		xnor_gate.vhd
xnor_gate_32.vhd		xnor_gate_32.vhd
xnor_gate_n.vhd		xnor_gate_n.vhd
xor_gate.vhd		xor_gate.vhd
xor_gate_32.vhd		xor_gate_32.vhd
xor_gate_n.vhd		xor_gate_n.vhd

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