Merge pull request #2146 from ucb-bar/i2c-fix

Add I2C peripheral example
ucb-bar · Dec 6, 2024 · dd2ce08 · dd2ce08
2 parents d4ebf93 + af63872
commit dd2ce08
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Showing 4 changed files with 19 additions and 3 deletions.
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -22,6 +22,7 @@ class AbstractConfig extends Config(
   new chipyard.harness.WithSimDMI ++                               /** add SimJTAG if DMI exposed */
   new chipyard.harness.WithGPIOPinsTiedOff ++                      /** tie-off chiptop GPIO-pins, if GPIO-punchthrough is used */
   new chipyard.harness.WithGPIOTiedOff ++                          /** tie-off chiptop GPIOs, if GPIOs are present */
+  new chipyard.harness.WithI2CTiedOff ++                           /** tie-off i2c ports if present */
   new chipyard.harness.WithSimSPIFlashModel ++                     /** add simulated SPI flash memory, if SPI is enabled */
   new chipyard.harness.WithSimAXIMMIO ++                           /** add SimAXIMem for axi4 mmio port, if enabled */
   new chipyard.harness.WithTieOffInterrupts ++                     /** tie-off interrupt ports, if present */

diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -19,6 +19,12 @@ class SmallSPIFlashRocketConfig extends Config(
   new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
+class I2CRocketConfig extends Config(
+  new chipyard.harness.WithI2CTiedOff ++                    // Tie off the I2C port in the harness
+  new chipyard.config.WithI2C ++                            // Add I2C peripheral
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
+  new chipyard.config.AbstractConfig)
+
 class SimBlockDeviceRocketConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++                // drive block-device IOs with SimBlockDevice
   new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to peripherybus
@@ -71,12 +77,15 @@ class dmiCospikeCheckpointingRocketConfig extends Config(
 
 
 class ManyPeripheralsRocketConfig extends Config(
+  new chipyard.harness.WithI2CTiedOff ++                    // Tie off the I2C port in the harness
+  new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
+  new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
+
   new testchipip.iceblk.WithBlockDevice ++                   // add block-device module to peripherybus
   new testchipip.soc.WithOffchipBusClient(MBUS) ++           // OBUS provides backing memory to the MBUS
   new testchipip.soc.WithOffchipBus ++                       // OBUS must exist for serial-tl to master off-chip memory
   new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
-  new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
-  new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
+  new chipyard.config.WithI2C ++                             // Add I2C peripheral
   new chipyard.config.WithPeripheryTimer ++                  // add the pwm timer device
   new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port

diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -75,6 +75,12 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends HarnessBinder({
   }
 })
 
+class WithI2CTiedOff extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: I2CPort, chipId: Int) => {
+    port.io <> DontCare
+  }
+})
+
 class WithSimBlockDevice extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: BlockDevicePort, chipId: Int) => {
     val sim_blkdev = Module(new SimBlockDevice(port.params))

diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -206,7 +206,7 @@ class WithI2CPunchthrough extends OverrideIOBinder({
     val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
       val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
       io_i2c <> i2c
-      I2CPort(() => i2c)
+      I2CPort(() => io_i2c)
     }
     (ports, Nil)
   }