This project involves designing and simulating a 6-bit fully differential current-steering Digital-to-Analog Converter (DAC) using LTSpice. The design focuses on achieving linearity and power efficiency while meeting key specifications.
- Process Technology: 180 nm
- Analog Supply Voltage: 1.8 V
- Full-Scale Voltage (pk-to-pk): 1.6 V
- Analog Input Range: 0 - 1.6 V
- INL (MAX): 0.5 LSB
- DNL (MAX): 0.5 LSB
- Maximum Static Power: < 1 mW
- Ideal Current Source Design:
- Used ideal current sources to implement the DAC and plotted transfer characteristics.
- PMOS Current Source Design:
- Replaced ideal sources with PMOS current sources, integrated with a row-column decoder.
- Simulated transfer characteristics, INL, and DNL.
Results can be found in the Results folder:
- Transfer Characteristics: Ideal vs Non-Ideal DAC.
- INL and DNL Plots: Analyze linearity performance.
Example output plots:
-
Ideal DAC Transfer Characteristic
-
Non-Ideal DAC Transfer Characteristic
-
INL
-
DNL
- Models Folder: Contains PMOS and NMOS models (
tsmc018.lib) required for simulation. - Ensure the
.libfile is included in the LTSpice schematic to run simulations successfully.
-
Install LTSpice:
Download and install LTSpice if not already installed. -
Set Up Models:
- Copy the
tsmc018.libfile from the Resources folder. - Include the
.libfile in your circuit schematic (use.include tsmc018.libin LTSpice).
- Copy the
-
Run Simulations:
- Open the LTSpice files (
diff_ideal_dac2.asc,r_cDAC.asc) in LTSpice. - Run the simulation to generate transfer characteristics, INL, and DNL plots.
- Open the LTSpice files (
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View Results:
- Check the generated results or refer to the pre-saved plots in the Results folder.
The design meets specified performance targets, with INL and DNL under 0.5 LSB. The results validate the effectiveness of the ideal and non-ideal DAC implementations.