feat(trap): support atomic instructions emulation

Cargo.toml

@@ -14,7 +14,7 @@ hpm-rt = { git = "https://github.com/hpm-rs/hpm-rt.git", rev = "66ffb7d7a65d7251
 riscv = "0.10"
 spin = "0.9"
 fast-trap = { version = "0.0.1", features = ["riscv-m"] }
-riscv-decode = "0.2.1"
+riscv-decode = { git = "https://github.com/fintelia/riscv-decode.git", rev = "349b2a6b9fa608fc427aa46eaef8935557510d28" }
 
 [build-dependencies]
 hpm-rt = { git = "https://github.com/hpm-rs/hpm-rt.git", rev = "66ffb7d7a65d7251d0b47db9599d36cefc4d6703" }

src/loader.rs

@@ -47,7 +47,7 @@ impl BlobInfo {
     }
 }
 
-pub unsafe fn load_test_kernel() {
+pub unsafe fn load_kernel() {
     let info: &BlobInfo = &BLOB_TABLE[0];
     assert!(info.type_ == BlobType::Kernel);
     assert!(info.start + info.length <= BLOB_TABLE[1].start);

src/main.rs

@@ -58,14 +58,14 @@ fn main() -> ! {
         firmware_address = _start as usize,
     );
     // 初始化 PMP
-    set_pmp();
+    pmp::set_pmp();
     // 显示 PMP 配置
     pmp::print_pmps();
     // 设置陷入栈
     trap_stack::prepare_for_trap();
     unsafe {
         // 加载内核
-        loader::load_test_kernel();
+        loader::load_kernel();
         // 加载设备树
         loader::load_dtb()
     };
@@ -84,6 +84,8 @@ fn main() -> ! {
         medeleg::clear_supervisor_env_call();
         medeleg::clear_illegal_instruction();
         medeleg::clear_machine_env_call();
+        medeleg::clear_store_fault();
+        medeleg::clear_load_fault();
         mtvec::write(fast_trap::trap_entry as _, mtvec::TrapMode::Direct);
         asm!("j {trap_handler}",
             trap_handler = sym fast_trap::trap_entry,
@@ -92,18 +94,6 @@ fn main() -> ! {
     }
 }
 
-/// 设置 PMP。
-fn set_pmp() {
-    use riscv::register::*;
-    unsafe {
-        // 1. SDRAM
-        pmpcfg0::set_pmp(0, Range::OFF, Permission::NONE, false);
-        pmpaddr0::write((0x4000_0000) >> 2);
-        pmpcfg0::set_pmp(1, Range::TOR, Permission::RWX, false);
-        pmpaddr1::write(usize::MAX >> 2);
-    }
-}
-
 #[panic_handler]
 fn panic(info: &core::panic::PanicInfo) -> ! {
     println!(

src/pmp.rs

@@ -1,4 +1,15 @@
 use crate::println;
+use riscv::register::*;
+
+pub fn set_pmp() {
+    unsafe {
+        // 1. SDRAM
+        pmpcfg0::set_pmp(0, Range::OFF, Permission::NONE, false);
+        pmpaddr0::write((0x4000_0000) >> 2);
+        pmpcfg0::set_pmp(1, Range::TOR, Permission::RWX, false);
+        pmpaddr1::write(usize::MAX >> 2);
+    }
+}
 
 pub(crate) fn print_pmps() {
     const ITEM_PER_CFG: usize = core::mem::size_of::<usize>();
@@ -47,7 +58,6 @@ fn dump_pmp(i: usize, s: usize, e: usize, cfg: usize) {
 }
 
 fn pmpcfg(i: usize) -> usize {
-    use riscv::register::*;
     match i {
         0 => pmpcfg0::read().bits,
         #[cfg(target_arch = "riscv32")]
@@ -60,7 +70,6 @@ fn pmpcfg(i: usize) -> usize {
 }
 
 fn pmpaddr(i: usize) -> usize {
-    use riscv::register::*;
     match i {
         0x0 => pmpaddr0::read(),
         0x1 => pmpaddr1::read(),

src/riscv_spec.rs

@@ -1,7 +1,7 @@
 #![allow(unused, missing_docs)]
 
-pub const CSR_TIME: u32 = 0xc01;
-pub const CSR_TIMEH: u32 = 0xc81;
+pub const CSR_TIME: usize = 0xc01;
+pub const CSR_TIMEH: usize = 0xc81;
 
 pub mod mie {
     use core::arch::asm;
@@ -102,3 +102,8 @@ pub mod mdcause {
         bits
     }
 }
+
+#[inline(always)]
+pub unsafe fn fence_i() {
+    core::arch::asm!("fence.i");
+}