Fully support the Write-Back mode of the HPDcache in the CVA6 #2691
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Hi @JeanRochCoulon, All Github tests are passing and almost all Thales's Gitlab tests too, except for the "HW config vcs-uvm cv32a65x" test. However, I do not have any log file to analyze what is failing. Could you please share with me any output file that I could analyze to solve the issue ? Thank you ! |
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Thank you @JeanRochCoulon. I did not update the Python configuration generator. I'll do that. |
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@JeanRochCoulon, now the issue is with the "ASIC Synthesis cv32a65x" test. Again no report is given. Could you please share the log file ? Thank you |
* There are new cache subsystem subtypes: HPDCACHE_WT, HPDCACHE_WB, or
HPDCACHE_WT_WB
* HPDCACHE_WT uses the HPDcache with the write-through policy
* HPDCACHE_WB uses the HPDcache with the write-back policy
* HPDCACHE_WT_WB uses the HPDcache with both write-trough and
write-back policies
* New parameter to indicate if the Dcache shall be flushed on a fence
instruction
* New parameter to indicate if the Dcache shall be invalidated after
flushing the cachelines
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Hello @cfuguet , During synthesis with VCS we have : Error: /home/gchauvon/rhel8/cva6/core/cache_subsystem/cva6_hpdcache_if_adapter.sv:142: The construct 'enum declaration inside generate' is not supported. (VER-721) |
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Thank you @Gchauvon for the error messages ! I've made a new push to fix the syntax unsupported by VCS |
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All good now ! |
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We get a HPDCache WB Now, GREAAAT !! |
This PR modifies some components in the CVA6 to fully support the WB mode of the HPDcache.
When on WB mode, there may be coherency issues between the Instruction Cache and the Data Cache. This may happen when the software writes on instruction segments (e.g. to relocate a code in memory).
This PR contains the following modifications:
In addition, it also fixes some issues with the rvfi_mem_paddr signal from the store_buffer.